Modern high performance out-of-order (speculative) executing microprocessors execute loads and stores out-of-order. There are occasions during the processing whereby a load may be erroneously executed before it has seen the correct interlocking store. When such occasions are detected, the errant load is re-executed by resyncing so that the load and all younger instructions in the pipeline are flushed. Although this ensures that load instructions are correctly executed, each of these resyncs wastes an execution opportunity, resulting in loss of performance.
FIG. 1 shows a conventional out-of-order executing microprocessor 100. The microprocessor 100 includes an integer fetch unit (IFU) 105, an instruction decoder 110, an instruction scheduler 115, a register file 120, an arithmetic and logic unit (ALU) 125, a write back unit (WBU) 130, an address generation unit (AGU) 135, a load store unit (LSU) 140, and a memory 145.
Still referring to FIG. 1, as an ongoing process, the IFU 105 sends instruction/address requests 150 that request an external memory 155 to send instruction bytes 160 from particular addresses. The IFU 105 outputs the instruction bytes 160 to the instruction decoder 110, which decodes the instruction bytes 160 such that each instruction is uniquely identified by a certain combination of bits. The instruction decoder 110 has the knowledge to interpret these instructions and, for example, determine whether an instruction is performing an “add” or a “multiply” function.
The instruction decoder 110 outputs decoded instructions 162 to the instruction scheduler 115, which orchestrates the order (i.e., scheduling) of the decoded instructions, and outputs ordered decoded instructions 164 to the register file 120. The register file 120 provides operands 166 for executing the ordered decoded instructions 164 to the ALU 125 and the AGU 135. The ALU 125 executes simple instructions which do not involve memory, (i.e., instructions which are purely arithmetical or purely logical and do not involve memory), and outputs execution results 168 to the WBU 130.
The WBU 130 essentially feeds back the execution results (by outputting feedback execution results 170) to the register file 120, after determining which addresses in the register file 120 to store the feedback execution results 170. The AGU 135 generates value addresses 174 to fetch values from the memory 145, and inputs the value addresses 174 to the LSU 140. The LSU 140 receives the value addresses 174 from the AGU 135, and also receives stored data results 176 from the register file 120, and determines the order in which the value addresses 174 are sent to the memory 145, such that the memory 145 fetches data located at particular addresses. The LSU 140 outputs the stored data results 176 to the memory 145 to write data, and outputs data/address requests 178 to the memory 145 to read data. The memory 145 outputs execution byte results 180 to the register file 120.
The responsibility of the LSU 140 is to schedule instructions to memory in an efficient way, such that overall performance of a system is satisfactory. The AGU 135 provides value addresses 174 to the LSU 140 that are not in a particular order. It is the responsibility of the LSU 140 to make sure that when it communicates with the memory 145, it does so in a methodical order to provide error-free execution results without reducing efficiency. However, since the LSU 140 in the microprocessor 100 of FIG. 1 typically executes instructions in a particular order, the LSU 140 is constrained from maximizing efficiency and performance.
A value address is essentially a request to memory to fetch data from a particular address. A store address is essentially a request to memory to write data to a particular event.
For example, if there exists a series of compilations whereby a first instruction indicates that c=a+b, and a second instruction indicates that e=2c+d, it is essential that the first instruction be executed before the second instruction. Otherwise, an error will occur.
If data is written in a particular memory location, followed by a read from that memory location, it is important to ensure that the data being read is the same data that was previously written. However, it is possible that the LSU 140 in the microprocessor 100 of FIG. 1 does not know what data is going to be written to another memory location that it wants to read. The LSU 140 may wait to make sure that all older stores have been written to memory before reading the data, which results in an undesired delay. Thus, every time a reading process from a different memory address begins, the probability of an error occurring is heightened.